A phase-locked loop is an electronic system used to lock the instantaneous phase of an electronic output signal, originating from this phase-locked loop, to the instantaneous phase of an electronic input signal (reference signal) received by this same phase-locked loop. However, it is also used to lock a frequency of the output signal to a multiple of the frequency of the input signal. A phase-locked loop proceeds by incrementation or decrementation, of the frequency of a clock signal supplied by an internal oscillator, according to the phase shift that exists between the input and output signals.
A conventional phase-locked loop usually comprises a phase comparator receiving the reference signal and a second signal originating from the output signal, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider.
A fractionary phase-locked loop differs from a conventional phase-locked loop in that, instead of an integer division ratio frequency divider, it comprises a fractionary frequency divider, that is to say with a division that is not integer.
There are several, more or less robust, and/or more or less time-consuming and space-consuming ways of detecting the locking of a phase-locked loop.
A first known approach includes applying a frequency model by using two counters counting respectively the payload edges of each of the two input signals in the phase comparator, namely the reference signal and the second signal (or the comparison signal originating) from the frequency divider.
In this type of locking detection model, since the averages of the frequencies are compared, the reference and comparison signals are analyzed for a relatively long time in order to improve the probability of stability of the comparison signal, and therefore the probability that the phase-locked loop will be properly locked. Because of the time used to detect locking, this type of detection model may delay the starting of the system controlled by the phase-locked loop. Moreover, the more important the accuracy of desired detection, the more space the counters used for the reference signal and for the comparison signal take up in the device.
A second approach that is also known includes using two D flip-flops with delays imposed by a capacitor load, and an AND logic port.
The systems for detecting the locking of a phase-locked loop of this type pose issues with robustness relative to variations in production process, voltage and temperature, and are subject to phenomena of local overvoltage (known as “glitches”), thereby adversely affecting the accuracy of detection which is highly dependent on the variation of these parameters. For a fractionary PLL, the division is not integer division and is therefore not constant. Since the ratio changes, the instantaneous period is not fixed. This gives the impression that the PLL is not locked.
A third known approach involves using a counter which makes it possible to disable the output of the phase-locked loop for a fixed time and to consider the PLL locked after this fixed time without analyzing the signals, which may sometimes be false.
However, the devices based on this approach are time-consuming for the phase-locked loop and costly in terms of physical space occupied. Furthermore, these devices also pose problems of robustness relative to variations in production process, voltage and temperature.